1. Technical Field
The present invention relates generally to chip guard rings for integrated circuits and, more particularly, to noise isolation for an integrated circuit using multiple chip guard rings.
2. Related Art
A chip guard ring is a protective metal structure and substrate contact encircling an entire active region of a chip. In some instances, a chip guard ring is referred to as a seal ring. Chip guard rings are provided as barriers to ionic contamination that can penetrate the exposed edges of a diced chip during manufacture, and for mechanical stability.
In conventional integrated circuits (ICs) where multiple circuit sections with differing characteristics are provided, certain sections must be isolated from other sections. Historically, a single chip guard ring is provided about all active circuit sections during manufacture regardless of their differing characteristics. A single chip guard ring, however, does not promote isolation between circuit sections. For example, where mixed digital and analog circuit sections are provided, isolation is required to reduce noise propagation. A single chip guard ring propagates noise readily from one section to another. In larger ICs (e.g., SoC type), the noise travels easily and causes many unwanted and unmanageable noise coupling situations. This situation is especially troublesome in wire bond ICs where floor planning with respect to the bond pads is restricted for radio frequency (RF) designs. Another example of where isolation is required is where different circuit voltage domains are used between sections. Again, a single chip guard ring hinders isolation between these sections.
One remedy that has been implemented relative to isolating different characteristic circuit sections is spacing the sections farther apart within the single chip guard ring. This solution, however, generates a number of unsatisfactory results. In particular, it increases space requirements, which is always a detriment to overall IC compactness; increases cost by reducing the number of chips per wafer; and is not always usable in wirebond ICs. Other remedies such as providing numerous grounds have also been proposed, but none adequately isolate or minimize the above-described side effects.
In view of the foregoing, there is a need in the art to overcome the lack of isolation for circuit sections having differing characteristics created by the use of a single chip guard ring.
The invention includes an integrated circuit having structure for isolating circuit sections having differing characteristics, e.g., a mixed analog and digital technology using multiple chip guard rings. The structure includes a chip guard ring for each circuit section having at least one different characteristic. Providing multiple chip guard rings isolates the circuit sections having different characteristics and provides the necessary barrier to ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also includes at least one interconnect about a chip guard ring to accommodate electrical connection to a circuit section therein.
A first aspect of the invention is directed to a structure for isolating circuit sections of an integrated circuit, the circuit sections each having at least one differing characteristic, the structure comprising: a chip guard ring for each circuit section having the at least one differing characteristic.
A second aspect of the invention is directed to an integrated circuit comprising: a first circuit section; a second circuit section having at least one different characteristic than the first circuit section; a first chip guard ring surrounding the first circuit section; and a second chip guard ring surrounding the second circuit section.
A third aspect of the invention is directed to a structure for an integrated circuit having a chip guard ring, the structure comprising: at least one interconnect for electrical connectivity about the chip guard ring.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.